[Bf-cycles] Req: Access to new branch for rendering on Intel Xeon Phi

Jaros Milan milan.jaros at vsb.cz
Wed Jul 26 10:58:41 CEST 2017


Hi Sergey,

 

-          Last time i looked into ISPC compiler examples, they were requiring adding some special hints on loops and such for an extra vectorization. Is that still a case ?

I have to make more tests, because I use OpenMP now. But writing a code is much easier than writing intrisics code. We can use this compiler only for kernels (like NVCC). I will check how it looks with the future of ISPC compiler - GCC compiler has still big problem with SIMD vectorization.

 

-          Is it only Xeon Phi architecture which will benefit from ISPC ?

ISPC is not only for Phi. It could bring the benefit for new CPUs. It currently supports the SSE2, SSE4, AVX1, AVX2, AVX512, and Xeon Phi "Knight's Corner" instruction sets.

 

-          AFAIR, Xeon Phi supports OpenCL, did you try that?

Yes (two years ago), but it was slower than OpenMP and I had to disable shaders. Now, Intel does not support this technology for Xeon Phi. I think this technology is the best only for AMD devices.

 

-          How's Xeon Phi performance compares to GTX1080 and RX480 ?

The Xeon Phi has same features like CPU (for example Cosmos Laundromat and Agent327 could be rendered on this type of devices). I think there is some functionality which OpenCL or CUDA does not support. GPUs have less memory. 

KNC is slower (OpenMP without KNC vectorization), but KNL will be faster (OpenMP without AVX512 vectorization). The NVIDIA now developing OpenACC which is similar to OpenMP directives.

 

Best regards

Milan

 

 

 

Milan Jaroš 

Research Assistant

 

IT4Innovations national supercomputing center

VŠB – Technical University of Ostrava

17. listopadu 15/2172  |   708 33 Ostrava-Poruba   |   Czech Republic

 

e-mail:  <mailto:milan.jaros at vsb.cz> milan.jaros at vsb.cz  |   web: industry.it4i.cz   |    phone: +420 597 329 583   |    map:  <http://goo.gl/maps/BpF0z> goo.gl/maps/BpF0z

 

 

From: bf-cycles-bounces at blender.org [mailto:bf-cycles-bounces at blender.org] On Behalf Of Sergey Sharybin
Sent: Sunday, July 23, 2017 4:07 PM
To: Discussion list to assist Cycles render engine developers <bf-cycles at blender.org>
Subject: Re: [Bf-cycles] Req: Access to new branch for rendering on Intel Xeon Phi

 

Hi,

 

The main issue i see here is that there's really a few Blender users who has Xeon Phi, and yet requesting to support it in Blender itself would mean complicating release builds (extra compiler etc), and opening can of worms of extra obscure bug reports on platforms which Blender/Cycles developers has no access to.

 

Some questions:

- Last time i looked into ISPC compiler examples, they were requiring adding some special hints on loops and such for an extra vectorization. Is that still a case ?

- Is it only Xeon Phi architecture which will benefit from ISPC ?

- AFAIR, Xeon Phi supports OpenCL, did you try that ?

- How's Xeon Phi performance compares to GTX1080 and RX480 ?

 

As for tile size, details about this better be discussed in separate topic i think. Otherwise we'll mix too many things in this discussion.

 

But once again, those are concerns about having this device enabled in Blender builds. If those are a compile-time option, with minimal changes outside of device/ and kernel entrypoints i'm not really against extra devices support.

 

 

On Sun, Jul 23, 2017 at 3:32 PM, Jaros Milan <milan.jaros at vsb.cz <mailto:milan.jaros at vsb.cz> > wrote:

Hi, 

 

I would like to create a new computed devices for Intel Xeon Phi (KNC, KNL).

 

I used my version of new computed devices for rendering of almost all scenes of Agent327 (http://blender.it4i.cz/rendering/agent-327-operation-barbershop/).

 

You can find more information here: http://blender.it4i.cz/research/rendering-on-intel-xeon-phi/

 

Now I use Intel compiler but I would like to change it to ISPC open sorce compiler.

 

I would like to open question about size of tiles for hybrid system CPU+CUDA/Phi ( CUDA, OpenCL, OpenMP require bigger tile than CPU ). Sergey has the some idea about this.

 

Thanks.

Best regards

Milan Jaroš
Research Assistant

IT4Innovations national supercomputing center
VŠB – Technical University of Ostrava

17. listopadu 15/2172  |   708 33 Ostrava-Poruba   |   Czech Republic

 

e-mail: milan.jaros at vsb.cz <mailto:milan.jaros at vsb.cz>   |   web: industry.it4i.cz <http://industry.it4i.cz>    |   phone: +420 <tel:+420%20597%20329%20583>  597 329 583   |    map: goo.gl/maps/BpF0z <http://goo.gl/maps/BpF0z> 


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-- 

With best regards, Sergey Sharybin

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