[Bf-blender-cvs] [468d59e496e] master: Add support for RISC-V architecture

[Heinrich Schuchardt]

Commit: 468d59e496eb3263c1b0284459c03b599fe84a2a
Author: Heinrich Schuchardt
Date:   Thu Jul 15 14:22:08 2021 +0200
Branches: master
https://developer.blender.org/rB468d59e496eb3263c1b0284459c03b599fe84a2a

Add support for RISC-V architecture

* On RISC-V GCC 10.3 does not define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_n.
* Avoid a build error
  "Please add support for your platform in build_config.h"
  Cf: https://github.com/sergeyvfx/libNumaAPI/pull/3

Differential Revision: https://developer.blender.org/D11910

===================================================================

M	intern/atomic/intern/atomic_ops_unix.h
M	intern/numaapi/source/build_config.h

===================================================================

diff --git a/intern/atomic/intern/atomic_ops_unix.h b/intern/atomic/intern/atomic_ops_unix.h
index dc1e71cda76..b08a0e9bc28 100644
--- a/intern/atomic/intern/atomic_ops_unix.h
+++ b/intern/atomic/intern/atomic_ops_unix.h
@@ -49,9 +49,9 @@
 
 #include "atomic_ops_utils.h"
 
-#if defined(__arm__)
-/* Attempt to fix compilation error on Debian armel kernel.
- * arm7 architecture does have both 32 and 64bit atomics, however
+#if defined(__arm__) || defined(__riscv)
+/* Attempt to fix compilation error on Debian armel and RISC-V kernels.
+ * Both architectures do have both 32 and 64bit atomics, however
  * its gcc doesn't have __GCC_HAVE_SYNC_COMPARE_AND_SWAP_n defined.
  */
 #  define JE_FORCE_SYNC_COMPARE_AND_SWAP_1
diff --git a/intern/numaapi/source/build_config.h b/intern/numaapi/source/build_config.h
index fdd6ff704c3..49d82aa3e87 100644
--- a/intern/numaapi/source/build_config.h
+++ b/intern/numaapi/source/build_config.h
@@ -324,6 +324,16 @@
 #  define ARCH_CPU_ARM64 1
 #  define ARCH_CPU_64_BITS 1
 #  define ARCH_CPU_LITTLE_ENDIAN 1
+#elif defined(__riscv) && __riscv_xlen == 32
+#  define ARCH_CPU_RISCV_FAMILY 1
+#  define ARCH_CPU_RISCV32 1
+#  define ARCH_CPU_64_BITS 0
+#  define ARCH_CPU_LITTLE_ENDIAN 1
+#elif defined(__riscv) && __riscv_xlen == 64
+#  define ARCH_CPU_RISCV_FAMILY 1
+#  define ARCH_CPU_RISCV64 1
+#  define ARCH_CPU_64_BITS 1
+#  define ARCH_CPU_LITTLE_ENDIAN 1
 #elif defined(__pnacl__) || defined(__asmjs__) || defined(__wasm__)
 #  define ARCH_CPU_32_BITS 1
 #  define ARCH_CPU_LITTLE_ENDIAN 1
@@ -381,6 +391,9 @@
 #if !defined(ARCH_CPU_PPC64_FAMILY)
 #  define ARCH_CPU_PPC64_FAMILY 0
 #endif
+#if !defined(ARCH_CPU_RISCV_FAMILY)
+#  define ARCH_CPU_RISCV_FAMILY 0
+#endif
 #if !defined(ARCH_CPU_S390_FAMILY)
 #  define ARCH_CPU_S390_FAMILY 0
 #endif