<div dir="ltr">Hi,<div><br></div><div>Answers are inlined,</div><div class="gmail_extra"><br><div class="gmail_quote"><br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div lang="EN-US"><div class="gmail-m_2528811918848912915WordSection1"><p class="MsoNormal"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)"> </span>-<span style="font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman""> </span><u></u>Last time i looked into ISPC compiler examples, they were requiring adding some special hints on loops and such for an extra vectorization. Is that still a case ?<br></p><span class="gmail-"><p class="gmail-m_2528811918848912915MsoListParagraph"><u></u></p></span><p class="MsoNormal"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)">I have to make more tests, because I use OpenMP now. But writing a code is much easier than writing intrisics code. We can use this compiler only for kernels (like NVCC). I will check how it looks with the future of ISPC compiler - GCC compiler has still big problem with SIMD vectorization.</span></p></div></div></blockquote><div><br></div><div>I am not a believer that compiler can do optimal intrinsics on its's own. We would still need to have math utilities implemented in explicit iinstrinsics. And since that's something we need to do anyway, i'm not sure why SIMD vectorization of GCC is listed as a concern here?</div><div><br></div><div>Question was more about whether it is required to have some ISPC syntax constructions in the kernel, to get optimal performance. For example, there are special versions of loops there. Trying to use them in kernel might make code tricky for other platforms. Or you'll end up with some ISPC specific kernel sources.</div><div><br></div><div>How would that work? Can you elaborate a bit more on this topic?</div><div><br></div><div>Also, while we are on the compiler's intrinsics discussion. Did you compare CPU side performance of kernel compiled with ISPC and GCC? What would be the performance if we disable explicit intrinsics in kernel?</div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div lang="EN-US"><div class="gmail-m_2528811918848912915WordSection1"><p class="MsoNormal"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)"><u></u><u></u></span></p><span class="gmail-"><p class="MsoNormal"><u></u> -<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman""> </span><u></u>Is it only Xeon Phi architecture which will benefit from ISPC ?</p><p class="gmail-m_2528811918848912915MsoListParagraph"><u></u></p></span><p class="MsoNormal"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)">ISPC is not only for Phi. It could bring the benefit for new CPUs. It currently supports the SSE2, SSE4, AVX1, AVX2, AVX512, and Xeon Phi "Knight's Corner" instruction sets.</span></p></div></div></blockquote><div><br></div><div>Related to previous question, is it worth using ISPC for CPU implementation? How portable it is? Can you limit instruction set for ISPC, so we can run on older CPUs?</div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div lang="EN-US"><div class="gmail-m_2528811918848912915WordSection1"><p class="MsoNormal"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)"><u></u><u></u></span></p><span class="gmail-"><p class="gmail-m_2528811918848912915MsoListParagraph"><u></u> -<span style="font-variant-numeric:normal;font-stretch:normal;font-size:7pt;line-height:normal;font-family:"Times New Roman""> </span><u></u>How's Xeon Phi performance compares to GTX1080 and RX480 ?</p></span><span class="gmail-"><p class="gmail-m_2528811918848912915MsoListParagraph"><u></u></p></span><p class="MsoNormal"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)">The Xeon Phi has same features like CPU (for example Cosmos Laundromat and Agent327 could be rendered on this type of devices). I think there is some functionality which OpenCL or CUDA does not support. GPUs have less memory. <u></u><u></u></span></p><p class="MsoNormal"><span style="font-size:11pt;font-family:Calibri,sans-serif;color:rgb(31,73,125)">KNC is slower (OpenMP without KNC vectorization), but KNL will be faster (OpenMP without AVX512 vectorization). The NVIDIA now developing OpenACC which is similar to OpenMP directives.</span></p></div></div></blockquote><div><br></div><div>It's not a question about feature set. It is a question about speed. The biggest missing feature is decoupled ray marching on GPU, but it is planned to fill that gap in. Memory i'm not sure is very relevant here. AMD GPUs are having 32Gb nowadays, and that figure will only increase. Surely, there might be more memory on Xeom Phi, but is it economically efficient for Blener/Cycles users, or they'd just stick to CPU side rendering?</div><div><br></div><div>All this depends on speed benefits users will have. The good estimate will come from benchmarks. Can you get numbers of scenes from our current benchmark bundle [1] ?</div><div><br></div><div>As for feature set, is it possible to get OSL to work on Xeon Phi?</div><div><br></div><div>[1] <a href="https://code.blender.org/2016/02/new-cycles-benchmark/">https://code.blender.org/2016/02/new-cycles-benchmark/</a></div></div><br clear="all"><div><br></div>-- <br><div class="gmail_signature"><div><span style="color:rgb(102,102,102)">With best regards, Sergey Sharybin</span></div></div>
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