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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><a name="_MailEndCompose"><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>Hi Sergey,<o:p></o:p></span></a></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'><o:p> </o:p></span></p><p class=MsoListParagraph style='text-indent:-18.0pt;mso-list:l0 level1 lfo1'><![if !supportLists]><span style='mso-list:Ignore'>-<span style='font:7.0pt "Times New Roman"'> </span></span><![endif]>Last time i looked into ISPC compiler examples, they were requiring adding some special hints on loops and such for an extra vectorization. Is that still a case ?<o:p></o:p></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>I have to make more tests, because I use OpenMP now. But writing a code is much easier than writing intrisics code. We can use this compiler only for kernels (like NVCC). I will check how it looks with the future of ISPC compiler - GCC compiler has still big problem with SIMD vectorization.<o:p></o:p></span></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoListParagraph style='text-indent:-18.0pt;mso-list:l0 level1 lfo1'><![if !supportLists]><span style='mso-list:Ignore'>-<span style='font:7.0pt "Times New Roman"'> </span></span><![endif]>Is it only Xeon Phi architecture which will benefit from ISPC ?<o:p></o:p></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>ISPC is not only for Phi. It could bring the benefit for new CPUs. It currently supports the SSE2, SSE4, AVX1, AVX2, AVX512, and Xeon Phi "Knight's Corner" instruction sets.<o:p></o:p></span></p><p class=MsoListParagraph><o:p> </o:p></p><p class=MsoListParagraph style='text-indent:-18.0pt;mso-list:l0 level1 lfo1'><![if !supportLists]><span style='mso-list:Ignore'>-<span style='font:7.0pt "Times New Roman"'> </span></span><![endif]>AFAIR, Xeon Phi supports OpenCL, did you try that?<o:p></o:p></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>Yes (two years ago), but it was slower than OpenMP and I had to disable shaders. Now, Intel does not support this technology for Xeon Phi. I think this technology is the best only for AMD devices.</span><o:p></o:p></p><p class=MsoListParagraph><o:p> </o:p></p><p class=MsoListParagraph style='text-indent:-18.0pt;mso-list:l0 level1 lfo1'><![if !supportLists]><span style='mso-list:Ignore'>-<span style='font:7.0pt "Times New Roman"'> </span></span><![endif]>How's Xeon Phi performance compares to GTX1080 and RX480 ?<o:p></o:p></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>The Xeon Phi has same features like CPU (for example Cosmos Laundromat and Agent327 could be rendered on this type of devices). I think there is some functionality which OpenCL or CUDA does not support. GPUs have less memory. <o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>KNC is slower (OpenMP without KNC vectorization), but KNL will be faster (OpenMP without AVX512 vectorization). The NVIDIA now developing OpenACC which is similar to OpenMP directives.</span><o:p></o:p></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span lang=CS style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>Best regards<o:p></o:p></span></p><p class=MsoNormal><span lang=CS style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'>Milan<o:p></o:p></span></p><p class=MsoNormal><span lang=CS style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span lang=CS style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span lang=CS style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal style='background:white'><b><span lang=CS style='font-size:10.0pt;font-family:"Arial",sans-serif;color:#24225A'>Milan Jaroš</span></b><span lang=CS style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:black'> <o:p></o:p></span></p><p class=MsoNormal style='background:white'><span lang=CS style='font-size:9.0pt;font-family:"Arial",sans-serif;color:#6A6A6C'>Research Assistant</span><span lang=CS style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:black'><o:p></o:p></span></p><p class=MsoNormal style='background:white'><span lang=CS style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:black'> <o:p></o:p></span></p><p class=MsoNormal style='background:white'><b><span lang=CS style='font-size:9.0pt;font-family:"Arial",sans-serif;color:#24225A'>IT4</span></b><b><span lang=CS style='font-size:9.0pt;font-family:"Arial",sans-serif;color:#009BDD'>Innovations</span></b><b><span lang=CS style='font-size:9.0pt;font-family:"Arial",sans-serif;color:#888888'> </span></b><b><span lang=CS style='font-size:9.0pt;font-family:"Arial",sans-serif;color:#AF1D1F'>national supercomputing center</span></b><span lang=CS style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:black'><o:p></o:p></span></p><p class=MsoNormal style='background:white'><span lang=CS style='font-size:9.0pt;font-family:"Arial",sans-serif;color:#888888'>VŠB – Technical University of Ostrava</span><span lang=CS style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:black'><o:p></o:p></span></p><p class=MsoNormal style='background:white'><span lang=CS style='font-size:9.0pt;font-family:"Arial",sans-serif;color:#888888'>17. listopadu 15/2172 | 708 33 Ostrava-Poruba | Czech Republic</span><span lang=CS style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:black'><o:p></o:p></span></p><p class=MsoNormal style='background:white'><span lang=CS style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:black'> <o:p></o:p></span></p><p class=MsoNormal><span lang=CS style='font-size:9.0pt;font-family:"Arial",sans-serif;color:#009BDD'>e-mail:</span><span lang=CS style='font-size:9.0pt;font-family:"Arial",sans-serif;color:#888888'> </span><a href="mailto:milan.jaros@vsb.cz" target="_blank"><span lang=CS style='font-size:9.0pt;font-family:"Arial",sans-serif'>milan.jaros@vsb.cz</span></a><span lang=CS style='font-size:9.0pt;font-family:"Arial",sans-serif;color:#888888'> | </span><span lang=CS style='font-size:9.0pt;font-family:"Arial",sans-serif;color:#009BDD'>web:</span><span lang=CS style='font-size:9.0pt;font-family:"Arial",sans-serif;color:#888888'> </span><a href="industry.it4i.cz"><span lang=CS style='font-size:9.0pt;font-family:"Arial",sans-serif;color:#0563C1'>industry.it4i.cz</span></a><span lang=CS style='font-size:9.0pt;font-family:"Arial",sans-serif;color:#888888'> | </span><span lang=CS style='font-size:9.0pt;font-family:"Arial",sans-serif;color:#009BDD'>phone:</span><span lang=CS style='font-size:9.0pt;font-family:"Arial",sans-serif;color:#888888'> +420 597 329 583 | </span><span lang=CS style='font-size:9.0pt;font-family:"Arial",sans-serif;color:#009BDD'>map: </span><a href="http://goo.gl/maps/BpF0z"><span lang=CS style='font-size:10.0pt;font-family:"Tahoma",sans-serif;color:#0563C1'>goo.gl/maps/BpF0z</span></a><span lang=CS style='font-size:10.0pt;font-family:"Tahoma",sans-serif;color:black'><o:p></o:p></span></p><p class=MsoNormal style='background:white'><span lang=CS style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:black'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><b><span lang=CS style='font-size:11.0pt;font-family:"Calibri",sans-serif'>From:</span></b><span lang=CS style='font-size:11.0pt;font-family:"Calibri",sans-serif'> bf-cycles-bounces@blender.org [mailto:bf-cycles-bounces@blender.org] <b>On Behalf Of </b>Sergey Sharybin<br><b>Sent:</b> Sunday, July 23, 2017 4:07 PM<br><b>To:</b> Discussion list to assist Cycles render engine developers <bf-cycles@blender.org><br><b>Subject:</b> Re: [Bf-cycles] Req: Access to new branch for rendering on Intel Xeon Phi<o:p></o:p></span></p><p class=MsoNormal><o:p> </o:p></p><div><p class=MsoNormal>Hi,<o:p></o:p></p><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>The main issue i see here is that there's really a few Blender users who has Xeon Phi, and yet requesting to support it in Blender itself would mean complicating release builds (extra compiler etc), and opening can of worms of extra obscure bug reports on platforms which Blender/Cycles developers has no access to.<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>Some questions:<o:p></o:p></p></div><div><p class=MsoNormal>- Last time i looked into ISPC compiler examples, they were requiring adding some special hints on loops and such for an extra vectorization. Is that still a case ?<o:p></o:p></p></div><div><p class=MsoNormal>- Is it only Xeon Phi architecture which will benefit from ISPC ?<o:p></o:p></p></div><div><p class=MsoNormal>- AFAIR, Xeon Phi supports OpenCL, did you try that ?<o:p></o:p></p></div><div><p class=MsoNormal>- How's Xeon Phi performance compares to GTX1080 and RX480 ?<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>As for tile size, details about this better be discussed in separate topic i think. Otherwise we'll mix too many things in this discussion.<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>But once again, those are concerns about having this device enabled in Blender builds. If those are a compile-time option, with minimal changes outside of device/ and kernel entrypoints i'm not really against extra devices support.<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div></div><div><p class=MsoNormal><o:p> </o:p></p><div><p class=MsoNormal>On Sun, Jul 23, 2017 at 3:32 PM, Jaros Milan <<a href="mailto:milan.jaros@vsb.cz" target="_blank">milan.jaros@vsb.cz</a>> wrote:<o:p></o:p></p><blockquote style='border:none;border-left:solid #CCCCCC 1.0pt;padding:0cm 0cm 0cm 6.0pt;margin-left:4.8pt;margin-right:0cm'><div><div><div><p class=MsoNormal><span style='font-size:10.5pt;font-family:"Arial",sans-serif'>Hi,</span> <o:p></o:p></p><div><p class=MsoNormal><span style='font-size:10.5pt;font-family:"Arial",sans-serif'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.5pt;font-family:"Arial",sans-serif'>I would like to create a new computed devices for Intel Xeon Phi (KNC, KNL).<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.5pt;font-family:"Arial",sans-serif'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.5pt;font-family:"Arial",sans-serif'>I used my version of new computed devices for rendering of almost all scenes of Agent327 (<a href="http://blender.it4i.cz/rendering/agent-327-operation-barbershop/" target="_blank">http://blender.it4i.cz/rendering/agent-327-operation-barbershop/</a>).<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.5pt;font-family:"Arial",sans-serif'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.5pt;font-family:"Arial",sans-serif'>You can find more information here: <a href="http://blender.it4i.cz/research/rendering-on-intel-xeon-phi/" target="_blank">http://blender.it4i.cz/research/rendering-on-intel-xeon-phi/</a><o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.5pt;font-family:"Arial",sans-serif'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.5pt;font-family:"Arial",sans-serif'>Now I use Intel compiler but I would like to change it to ISPC open sorce compiler.<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.5pt;font-family:"Arial",sans-serif'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.5pt;font-family:"Arial",sans-serif'>I would like to open question about size of tiles for hybrid system CPU+CUDA/Phi ( CUDA, OpenCL, OpenMP require bigger tile than CPU ). Sergey has the some idea about this.<o:p></o:p></span></p></div></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal style='margin-bottom:12.0pt'>Thanks.<o:p></o:p></p><div><p class=MsoNormal style='margin-bottom:12.0pt'>Best regards<br><br>Milan Jaroš<br>Research Assistant<br><br>IT4Innovations national supercomputing center<br>VŠB – Technical University of Ostrava<br><br>17. listopadu 15/2172 | 708 33 Ostrava-Poruba | Czech Republic<br><br> <br><br>e-mail: <a href="mailto:milan.jaros@vsb.cz" target="_blank">milan.jaros@vsb.cz</a> | web: <a href="http://industry.it4i.cz" target="_blank">industry.it4i.cz</a> | phone: <a href="tel:+420%20597%20329%20583" target="_blank">+420 597 329 583</a> | map: <a href="http://goo.gl/maps/BpF0z" target="_blank">goo.gl/maps/BpF0z</a><o:p></o:p></p></div></div></div></div><p class=MsoNormal style='margin-bottom:12.0pt'><br>_______________________________________________<br>Bf-cycles mailing list<br><a href="mailto:Bf-cycles@blender.org">Bf-cycles@blender.org</a><br><a href="https://lists.blender.org/mailman/listinfo/bf-cycles" target="_blank">https://lists.blender.org/mailman/listinfo/bf-cycles</a><o:p></o:p></p></blockquote></div><p class=MsoNormal><br><br clear=all><o:p></o:p></p><div><p class=MsoNormal><o:p> </o:p></p></div><p class=MsoNormal>-- <o:p></o:p></p><div><div><p class=MsoNormal><span style='color:#666666'>With best regards, Sergey Sharybin</span><o:p></o:p></p></div></div></div></div></body></html>